Metal-oxide-semiconductor field effect transistor (MOSFET) technology is the dominant semiconductor technology used for the manufacture of ultra-large scale integrated (ULSI) circuits. Reduction in the size of MOSFETs have provided continued improvement in speed performance, circuit density, and cost per unit function over the past few decades. As the gate length of the conventional bulk MOSFET is reduced, the source and drain increase interact with the channel and gain influence on the channel potential. Consequently, a transistor with a short gate length suffers from problems related to the inability of the gate to substantially control the on and off states of the channel. Phenomena such as reduced gate control associated with transistors with short channel lengths are termed short-channel effects. Increased body doping concentration, reduced gate oxide thickness, and ultra-shallow source/drain junctions are ways to suppress short-channel effects. However, for device scaling well into the sub-50 nm regime, the requirements for body-doping concentration, gate oxide thickness, and source/drain (S/D) doping profiles become increasingly difficult to meet when conventional device structures based on bulk silicon substrates are employed. Innovations in front-end process technologies or the introduction of alternative device structures are required to sustain the historical pace of scaling.
For device scaling well into the sub-30 nm regime, a promising approach for controlling short-channel effects is to use an alternative device structure with multiple-gate electrodes. Examples of multiple-gate structures include the double-gate structure, the triple-gate structure, the omega-FET structure, and the surround-gate or wrap-around gate structure. A multiple-gate transistor structure is expected to extend the scalability of CMOS technology beyond the limitations of the conventional bulk MOSFET and realize the ultimate limit of silicon MOSFETS. The introduction of additional gates improves the capacitance coupling between the gates and the channel, increases the control of the channel potential by the gate, helps to suppress short channel effects, and prolongs the scalability of the MOS transistor.
An example of a multiple-gate device is the double-gate MOSFET structure, wherein there are two gate electrodes on the opposing sides of the channel or silicon body. A method to fabricate a double-gate MOSFET is described in U.S. Pat. No. 6,413,802 B1 and shown in FIG. 1A for FinFET transistor structures 10 having a double gate channel extending vertically from a substrate and methods of manufacture. In U.S. Pat. No. 6,413,802 B1, the device channel includes a thin silicon fin 12 formed on an insulative substrate 14 (e.g., silicon oxide) and defined using an etchant mask 16. Gate oxidation is performed, followed by gate deposition and gate patterning to form a double-gate electrode 20 overlying the sides 22, 24 of the fin 12. Both the source-to-drain direction and the gate-to-gate direction are in the plane of the substrate surface. The device structure 10, an enlarged, cross-sectional view of which is illustrated in FIG. 1A, is widely recognized to be one of the most manufacturable double-gate structures. A plane view of the double-gate structure 10 is shown in FIG. 1C.
Another example of the multiple-gate transistor is the triple-gate transistor. An enlarged, cross-sectional view of the triple-gate transistor structure 30 is illustrated in FIG. 2A. A plane view of the triple-gate structure 30 is shown in FIG. 2C. The triple-gate transistor structure 30 has three gates: gate 32 on the top surface 42 of the silicon fin 12, and gates 34,36 on the sidewalls 44,46 of the silicon fin 12. The triple-gate structure 30 achieves better gate control than the double-gate device 10 because of the extra gate 32 on the top 42 of the silicon fin 12. The double-gate device structure 10 and the triple-gate device structure 30 may be improved by further enhancing the gate control.
An illustration of the cross-section of the double-gate device is shown in FIG. 1A. FIG. 2A illustrates the cross-section of the triple-gate device. Both the double-gate structure 10 and triple-gate structure 30 have a silicon body or fin 12 that overlies an insulator substrate 14. The double-gate device structure 10 (FIG. 1A) has a gate electrode 20 that wraps around the silicon fin 12 covered with a gate dielectric layer 26 on its two sidewalls 22,24. The gate electrode 20′ therefore forms two gates 34,36, one on each sidewall 22,24 of the silicon fin 12. For the triple-gate device structure 30 (FIG. 2A), the gate electrode 20 that wraps around the gate dielectric layer 26 covered silicon fin 12 forms three gates: 34,36 gate 32 on the top surface 42 of the silicon fin 12, and two gates 34,36 on the sidewalls 22,24 of the silicon fin 12.
The double-gate device structure 10 and the triple-gate device structure 30 may be improved by further enhancing the gate control. For example, the gate electrode 20 in the double-gate structure 40 may encroach under the silicon fin 12 forming an undercut 28 as shown in FIG. 1B. For the triple-gate structure 50, the gate electrode 20 may also encroach under the silicon fin 12 as shown in FIG. 2B. For the triple-gate structure 50, the encroachment of the gate electrode 20 under the silicon fin 12 forms an omega-shaped gate structure. This improved triple-gate transistor structure 50, also called the Omega field-effect transistor (FET), has the closest resemblance to the Gate-All-Around (GAA) transistor for excellent scalability, and uses a very manufacturable process similar to that for the double-gate or triple-gate transistor. The Omega-FET has a top gate like the conventional ultra-thin body silicon-on-insulator transistor, sidewall gates like double-gate transistors, and special gate extensions or encroachments under the silicon body. The Omega-FET is therefore a field effect transistor with a gate that almost wraps around the body. In fact, the longer the gate extension, i.e., the greater the extent of the encroachment, the more the structure approaches or resembles the gate-all-around structure. A three-dimensional perspective of an Omega-FET 50 is shown in FIG. 3.
The encroachment of the gate electrode under the silicon body helps to shield the channel from electric field lines from the drain and improves gate-to-channel controllability, thus alleviating the drain-induced barrier lowering effect and improving short-channel performance. The encroachment of the gate electrode under the silicon body relies on an undercut of the insulator layer in the substrate, thus forming a notch in the substrate at the base of the silicon body.
A simple process flow for fabricating the multiple-gate structure 50 with an omega-shaped electrode 20 is shown in FIGS. 4A-4C. It provides a vertical semiconductor fin 12 overlying a substrate 18 including a surface insulator layer 14. A cross-section of the fin 12 is shown in FIG. 4A. An undercut 28 in the insulator layer 14 of the substrate 18 is formed by an etch process, as shown in FIG. 4B. For example, if the insulator 14 is silicon oxide, the etch may be performed by a wet etch using diluted hydrofluoric acid (HF) (for example, a mixture of 25 parts of water and 1 part of concentrated HF) for 60 seconds at 25 degrees Celsius to achieve a recess “R” of about 100 angstroms. The etch process also etches laterally, resulting in an undercut 28 below the silicon fin 12. However, such a timed etch is not a very controllable process and introduces significant variability of the value of recess R within wafer and from process run to run. After formation of the substrate recess, the gate dielectric layer 26, gate electrode 20 (FIG. 4C), and source/drain regions 52,54 are formed to complete the device fabrication. It is important to limit the variability of the recess R in a manufacturing process as this affects the tolerance in the subsequent gate etch process.
It is therefore an object of the present invention to provide a method for forming a double-gate transistor with improved gate control.
It is another object of the present invention to provide a method for forming a triple-gate transistor with improved gate control.